HIGH PERFORMANCE ARCHITECTURE

BluSP is a high performance DSC [mix of DSP and Controller] core.

• 3 Issue core architecture
• Single cycle complex MAC
• 600 MHz speed in a 40nm LP library

WIRELESS applications

Its calculation power and speed make it fit to implement also complex and high data rate modulation applications

It can e.g. handle a 256 point FFT in 1350 cycles with 16bit precision

Audio processing

Its 32 bit capability make it fit to handle audio applications

The core can implement in 32bit an MP3 decoder, running at 4 MHz clock rate

Ultra low power

The core consumes in a 40nm LP TSMC library, operated at 1.1Volts a current of 13uA/MHz with a typical program. It consumes 21uA/MHz with a “smoker” pattern. This pattern is loading the slots and the complex MAC at 100%

These data are based on simulations with post layout extraction of load capacitances and resistances

Software Development Kit

ECLIPSE based software development kit

Small, ultra RISC, instruction set with few [only one] specific data type -> makes it very easy to optimize standard C code for the core

Comprised of a [assembly] code simulator, debugger, profiler, compiler.

Developed in cooperation with an external partner.